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For ultimate MOSFET scaling, ultra thin body and BOX SOI transistors have become of great interest, as they are known to dramatically reduce short channel effects (SCE) while maintaining very high device performance. In this work, we emphasize the impact of the substrate / BOX interface space charge conditions on the drain induced barrier lowering (DIBL) increase with gate length reduction, as this...
In this paper we show for the 1st time that Silicon nanocrystal (Si-ncs) memories with high-k (HfO2, Al2O3 and HfAlO) interpoly dielectrics (IPD) can offer excellent behaviour in the Fowler-Nordheim regime, with great relevance for future sub-45 nm NAND memory generations. We significantly advance the state-of-the-art by showing a strict correlation between the different IPD properties and the performance...
This work presents TCAD simulations of NOR NC memories performed with commercial tools, which allow for a good understanding of the impact of the localized charge on both electrostatics and dynamics of the cell. The key role of the position of the trapped charges along the channel length on the threshold voltage shift has been put in evidence. Indeed, this result is critical for NOR discrete-trap...
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