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As memory speed goes up higher and I/O counts continue to increase, simulations estimating SSN-induced jitter are necessary for timing quality [1]. Traditional SSN-induced jitter simulation for high-density I/O designs normally calculates transient noise from multiple aggressors on one victim in one time domain simulation. Multiple number of simulations are required to ensure the signal pin with worst...
This paper analyzes high-speed interface simultaneous switching jitter (SSJ) and mathematically describes methods for reducing SSJ in number, spatial, time, and frequency dimensions. Quantitative relationships between SSJ and its major sources — SSO crosstalk, driver PDN SSN, and pre-driver PDN SSN — are discussed. Firmware and hardware methods for SSJ reduction on die, on package, and on PCB from...
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