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A Q-band DAHI (Diverse Accessible Heterogeneous Integration) multi-technology VCO-amplifier chain is presented. The DAHI integration process is composed of InP HBT, GaN HEMT and 65nm CMOS. The InP VCO demonstrated 2GHz of tuning range at 35GHz while the GaN amplifier provides 15dB gain.
A 45GHz 64QAM system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) is presented. The SoC includes a 7M gate ASIC with 9b reconfigurable symbol mapping, 8X upsampling, 161tap pulse shape filtering, IQ imbalance correction and DAPA envelope/time estimation. The ASIC feeds two 10b IQ current-steering DACs and active IQ modulator. A unique transformer splitting up converter...
A CMOS D-band 135–150 GHz transmitter is presented with integrated digital control and on-chip antenna. The proposed transmitter employs an IF feed-forward compensation scheme which improves the soft gain compression of the power amplifier by 5.1dB to provide an overall more linear AM-AM profile allowing reduced power back-off for modulation schemes with a high peak-to-average ratio. The proposed...
This paper presents a digitally controlled frequency synthesizer in 65nm CMOS technology for D-band transceiver applications. The synthesizer uses a low frequency U Band (44–48 GHz) phase-locked loop to track a 50 MHz reference and then employs an injection locked frequency tripler (ILFT) to provide output that can be tuned between 130 and 133 GHz. The proposed D-band synthesizer offers a directly...
We have realized a 200GHz 4×4 focal plane array (FPA) by using super-regenerative receiver (SRR) pixels made of 65nm CMOS for mm-wave imaging applications. With 16 pixel elements constructed on PCB, the FPA consumes 215mA under 1V power supply. Such realization is made possible by carefully analyzing the super-regenerative interference (SRI) commonly observed in close-spaced SRRs and applying a newly...
Large supply bouncing due to the fast switching current and parasitic inductance of the supply rail may cause reliability and electromagnetic interference (EMI) problems, especially for ICs with the pulse-width modulation (PWM) technique, such as switching DC-DC converters. In this paper, a new slew-rate controlled (SRC) output stage is proposed to appropriately increase the rise and fall times of...
We present the design and test results for D-band CMOS transmitter (Tx) and receiver (Rx) for ultra-high speed and short distance data communications. The Tx/Rx employs modulation/de-modulation based on Amplitude-Shift Keying (ASK) to facilitate a non-coherent data link without power-hungry PLL, data converters, and complex DSP. The Tx consists of a wideband 131~140GHz VCO along with an On/Off key...
A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting a 802.15.3c heterodyne TRX is reported. The PLL can generate 6 equally spaced tones from 43.2GHz to 51.84GHz, which is suitable for a heterodyne architecture with LO=(4/5)RF. Phase noise is measured directly at the LO frequency and is better than -97.5dBc/Hz@1MHz across the entire band. The total power consumption is...
An unique time-interleaved dual injection locking scheme has been devised to enable ultra high-speed and low-power frequency division with extended frequency locking range. To prove the concept, two frequency dividers (or prescalers) have been realized in 65nm digital CMOS: one divides continuously from 158GHz to 195GHz (or 21% locking range) with input signal <; 0dBm and the other divides from...
We present an integrated frequency synthesizer in 65nm CMOS to enable the 81-86GHz satellite communication transceiver. The frequency synthesizer is inserted in a two-step zero-IF millimeter-wave transceiver with LORF at 70-78GHz and LOIF at 1/8 of LORF to cover the desired entire frequency bands. It also features coarse phase rotation to endow beam forming capabilities for the intended communication...
A fully differential 60 GHz three-stage transformer-coupled amplifier is designed and implemented in 65 nm digital CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanisms, and simultaneous input/inter-stage/output matching networks are used to facilitate a compact circuit design. With a cascoded circuit configuration, the amplifier is tested...
A JPEG XR chip for HD-Photo is implemented with 25 mm2 area in TSMC 0.18 um CMOS 1P6M technology at 100 MHz. According to the simulation results, the 4:4:4 1920x1080 HD-Photo 20 frames/sec can be encoded smoothly.
A low power inductorless wideband variable gain control amplifier (VGA) for baseband receivers has been designed in a standard digital 90 nm CMOS technology. The VGA was implemented using four-stage modified Cherry-Hooper amplifier with a dual feedback DC-offset canceling network, which simultaneously corrects DC offsets and extends bandwidth without a peaking inductor resulting in saving the chip...
The chemical and plasma oxidation behaviors of NiSi and NiPtSi salicide films in a 65 nm node CMOS device fabrication process have been investigated. By incorporating Pt into the nickel salicide formation process, the oxidation rate can be effectively reduced during both salicidation etch/clean and contact plasma etch processes. Data collected from this study suggests both stronger chemical bonding...
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