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This paper presents an efficient design and implementation of a configurable multifunctional floating-point unit for the computation of division, reciprocal, square root and inverse square root, which is fully compatible with the IEEE754 standard. Based on the Newton-Raphson method and utilizing fast parallel multipliers, the design is fast, scalable, easy to pipeline, and has very high precision...
Register file is needed to work in high speed for high performance superscalar processors to execute multiple parallel instructions. A 10-read 6-write write-through register file, customized in 1.8V 0.18mum CMOS technology, is introduced here, every port of which can be accessed individually. It comprises two arrays of modified 16-port memory cells, some low-power SCL decoders and a local clock generator,...
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