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Modern system-on-chip designs implement sophisticated power management features to achieve better energy efficiency. This includes power-down modes for analog circuit blocks. Typically, they are implemented by additional power-down circuitry which shuts down all bias currents. During the design of power-down circuitry, it must be ensured that the circuit still meets all specifications in normal operation...
In order to reduce the power consumption of a system-on-chip, analog circuits can be switched off when not needed with the help of power-down switches. The power-down synthesis task comprises the structural synthesis of the power-down circuitry and switch sizing. A first approach for automatic structural synthesis was published recently. This paper completes the power-down synthesis task by an effective,...
In this paper, a new method for static analysis of the power-down mode of analog circuits is presented. Floating nodes are detected. The static node voltages are estimated. It can be verified that no current is flowing. The method is based on circuit structure. No numerical simulation is needed. The presented approach solves an integer constraint program. Experimental results show a speed-up of factor...
Due to the need for energy efficiency, power management features of modern systems on chips are becoming more and more complex. The complexity also affects analog/mixed-signal circuit blocks. They are equipped with power-down modes to shut off bias currents while the block is not used. In industrial practice, the power-down circuitry is added manually towards the end of the design phase. Due to the...
In this work, a new verification method for the power-down mode of analog circuit blocks is presented. In power-down mode, matched transistors can be stressed with asymmetric voltages. This will cause time-dependent mismatch due to transistor aging. In order to avoid reliability problems, a new method for automatic detection of asymmetric power-down stress conditions is presented. Therefore, power-down...
In this work, a method for aging-aware verification of analog circuits in power-down mode is presented. The core of the method is a voltage propagation algorithm that estimates node voltages based on circuit structure only. No numerical simulation is needed. This is crucial as simulation models are often unreliable in power-down mode. A precise graph-based formulation of the voltage propagation algorithm...
During analog design, the values of circuit parameters like transistor lengths and widths must be assigned, such that performance specifications are fulfilled for various operating conditions. Additionally, the design should be robust against process variations. The sizing must consider discrete design parameters, e.g., to model multipliers or manufacturing grids. Currently, no tools are available...
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