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Meaningless identifiers as well as inconsistent use of identifiers in the source code might hinder code readability and result in increased software maintenance efforts. Over the past years, effort has been devoted to promoting a consistent usage of identifiers across different parts of a system through approaches exploiting static code analysis and Natural Language Processing (NLP). These techniques...
This article investigates pin accessibility problem of standard cells designed with a sub-20nm technology. The 15nm open cell library from NanGate and three of its variants with a reduced number of access points per pin based on FreePDK15 are used for our study. Our experiments show that a standard cell library is viable when the number of access points per pin is not less than three.
As features in semiconductor technology become extremely scaled down, manufacturability is becoming a great challenge. Owing to the delayed adoption of new lithographic techniques, such as extreme ultraviolet (EUV), e-beam direct-write (EBDW), and directed self-assembly (DSA), in IC volume production, double patterning lithography (DPL) or multiple patterning lithography (MPL) is used to print critical...
This paper proposes a method to explore the design space of FinFETs with double fin heights. Our study shows that if one fin height is sufficiently larger than the other and the greatest common divisor of their equivalent transistor widths is small, the fin height pair will incur less width quantization effect and lead to better area efficiency. We design a standard cell library based on this technology...
This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counterparts. Only 11% of cells use more vias than their handcrafted counterparts. Our router completes routing...
This article presents a router, called Rover II, for via-configurable structured ASIC with mixed standard cells and relocatable IPs. Rover II extends the work of Rover and incorporates a porting of NTHU-Route 2.0 and NCTU-GR global routers. Experimental results show that Rover II can successfully route a via-configurable structured ASIC with standard cells and IPs under different routing fabrics....
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