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This paper presents the algorithm and architecture of the decimal floating-point (DFP) logarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP logarithm results for any one of the three DFP formats specified in the IEEE 754-2008 standard. In order to optimize the latency for the proposed design, we mainly integrate the...
This paper presents a parallel architecture of an QR decomposition systolic array based on the Givens rotations algorithm on FPGA. The proposed architecture adopts a direct mapping by 21 fixed-point CORDIC-based process units that can compute the QR decomposition for an 4×4 real matrix. In order to achieve a comprehensive resource and performance evaluation, the computational error analysis, the resource...
This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal antilogarithmic converter. A linear approximation algorithm is proposed and simulated in MATLAB models. The maximum absolute error of the proposed decimal antilogarithmic converter is in the range of -0.000999 les Eabsolute les 0.000857 and the maximum percent error is in the range of -0.000715 les Epercent...
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