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We report new developments on hybrid integration that attaches CMOS driver circuits to silicon photonic (SiPhotonic) devices built in Silicon on Insulator (SOI) technology. This low-parasitic hybrid integration approach enables energy efficient links based on aggressive silicon photonic devices and low power, high speed circuits. The silicon photonic components are fabricated in the 130 nm Cu node...
The technologies associated with integration and packaging have a significant impact on the overall system. In this paper, we review a silicon photonic “macrochip” system and its associated packaging that will allow dense wavelength-division multiplexed optical links to be intimately integrated and co-manufactured with the switching electronics. For this to happen, we anticipate a number of integration...
We report an ultra-low power 80 Gbps arrayed silicon photonic transceiver for dense, large bandwidth inter/intra-chip interconnects. The hybrid CMOS transceiver consists of eight 10 Gbps WDM channels with total consumed power below 6 mW/channel.
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