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Traditional spin transfer torque MRAM (STT-MRAM) uses one transistor and one MTJ (1T-1MTJ) architecture, where the transistor provides bi-polar currents to switch the magnetization of the free layer of the MTJ. Due to the limitation of the maximum current that is available from a typical transistor, for a MTJ device with required thermal stability and data retention at extreme densities, the size...
Intellectual property information service industry has obtained swift and dramatic development in recent years. However, the majority of intellectual property agencies are small or medium size enterprises which are small-scale, less funding and tech-support, scattered layout, and have strong demands. Cloud-computing as an emerging technology presents significance for small and medium-sized enterprises...
We investigate the use of the particle filtering sequential Bayesian estimation technique and its hardware implementation for tracking neural activity. We propose using the multiple particle filter (MPF) approach in order to reduce the computational intensity incurred due to the large number of sensors required to observe the noninvasive magnetoencephalography (MEG) measurements needed to estimate...
Sequential Monte Carlo particle filters (PFs) are useful for estimating nonlinear non-Gaussian dynamic system parameters. As these algorithms are recursive, their real-time implementation can be computationally complex. In this paper, we analyze the bottlenecks in existing parallel PF algorithms, and we propose a new approach that integrates parallel PFs with independent Metropolis-Hastings (PPF-IMH)...
Research into the limits of electrical interconnects indicates that metal wire is unlikely to be the ultimate solution to support the growing functionalities of next generation microprocessor. Severe information latency and power consumption are key technological challenges facing the traditional copper interconnects which impose tremendous constraints to keep up with the performance roadmap known...
Chip multi-processor exploits both instruction-level and thread-level parallelism effectively. In a typical chip multi-processor architecture, L2 cache is shared by multiple cores. Sharing the L2 cache allows high cache utilization and avoids duplicating cache hardware resources. Unfortunately, the mis-predictions of any processor core could lead the load miss from the wrong path to write some useless...
Peer-to-peer (P2P) file sharing networks attract much attention from legal and research communities. The success and popularity of P2P networks provides a new paradigm for sharing and distributing information. However, the widespread illegal distribution of the copyright protected works and anonymous malicious attacks to the network raise serious concerns for the future of P2P applications. Legal...
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