The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, the skew by data dependent gate loading has been analyzed. A method based on the concept of MOS parametric capacitance has been proposed. According to different data dependent of the MOS transistor, including transient channel charge and Miller effects, the values of capacitance in different data loadings have been extracted. Two clock tree routes have been analyzed by using the gate...
A JTAG IP core based on IEEE1149.1 standard has been reported here, including its design and implementation. It has been described using synthesized Verilog HDL language. Simulation demonstration has also been made and the result has been synthesized. It has been demonstrated that the IP core design is feasibility. Moreover, based on the characteristic of DFT using JTAG standard, some improvements...
In this paper, the skew by data dependent gate loading has been analysized. A method based on the concept of MOS parametric capacitance has been proposed. According to different data dependent of the MOS transistor, including transient channel charge and Miller effects, the values of capacitance in different data loadings have been extracted. Two clock tree routes have been analyzed by using the gate...
Continuous-time Delta-Sigma modulators are able to operate at higher frequencies than their discrete-time counterparts. However, they suffer more severely from non-idealities such as clock jitter. A method for measuring this clock jitter has been proposed. Moreover, the effect of the non-ideality are explained and a continuous-time to discrete-time conversion method is presented in order to aid in...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.