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This work proposes a new method of synthesizingasynchronous circuits targeting its practical usability. The keycontribution of this work is finding an effective technique ofinter-mixing the two design principles namely handshaking basedsingle-rail and timing annotated (i.e., delay insensitive) dual-railof asynchronous circuits. Precisely, we propose clever ways ofpartitioning an input (synchronous)...
In through-silicon-via (TSV) based 3-D integrated chips (ICs), synthesizing 3-D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, flip-flops) through TSVs, any fault on a TSV in the clock tree may cause a chip failure. Therefore, ensuring the reliability of clock TSVs in 3-D ICs is highly important. To cope with clock TSV reliability...
In TSV (Through-Silicon-Via) based 3D ICs, synthesizing 3D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, FFs) through TSVs, any fault on a TSV in the clock tree causes a chip failure. Therefore, ensuring the reliability of clock TSVs is highly important. Instead of the naive solution using double-TSV technique, which demands significant...
Recently, to cope with clock TSV (Through-Silicon-Via) reliability problem efficiently, a new circuit structure called TSV Fault-tolerant Unit (TFU) and the allocation method of TFUs have been proposed. However, the existing design methods partially or never addressed following key issues: (1) the feasibility of TSV pairing for TFU allocation, (2) maximizing TSV pairing, (3) supporting the slew and...
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