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Recent advances and new trends in high voltage SiC based MOSFETs are analyzed. The main focus is done on design optimization strategies for reducing the on-state resistance. Gate oxide treatments for improving the interface quality resulting in a lower channel resistance are reviewed as well as solutions for lowering the JFET and bulk resistance components. The 3rd quadrant operation, short-circuit...
It is well known from the literature published on Si devices that junction field effect transistors (JFETs) can be either operated in a unipolar mode (when the gate junction bias is less than 0.4 V) or in a bipolar mode (when the gate junction inject minority carriers into the channel/drift region to modulate its resistance)- The latter mode of operation is typically used to improve the on-state performance...
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