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Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level reconfigurable abstractions. Both fine-grain and coarse-grain architectures (e.g. CGRAs) traditionally require low level programming and suffer from long...
As technology is reaching physical limits, reducing power consumption is a key issue on our path to sustained performance. In this paper, we study fundamental tradeoffs and limits in efficiency (as measured in energy per operation) that can be achieved for an important class of kernels, namely the level-3 Basic Linear Algebra Subprograms (BLAS). It is well-accepted that specialization is the key to...
This paper introduces a new versatile and high-performance parallel hardware engine for matrix computations based on distributed memory. The proposed architecture reduces memory bandwidth by taking advantage of data redundancies. The core computes matrix power, multiplication, and inversion. The matrix power presented in this paper is mathematically proven to be two times faster than normal computations,...
This paper introduces a new versatile and high-performance parallel hardware engine for matrix computations. The proposed architecture reduces memory bandwidth by taking advantage of data redundancies and employing distributed memory structures. It is designed to better utilize the on chip area for computing different types of matrix computations such as matrix power, multiplication, and inversion...
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