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This paper introduces a new versatile and high-performance parallel hardware engine for matrix computations based on distributed memory. The proposed architecture reduces memory bandwidth by taking advantage of data redundancies. The core computes matrix power, multiplication, and inversion. The matrix power presented in this paper is mathematically proven to be two times faster than normal computations,...
This paper introduces a new versatile and high-performance parallel hardware engine for matrix computations. The proposed architecture reduces memory bandwidth by taking advantage of data redundancies and employing distributed memory structures. It is designed to better utilize the on chip area for computing different types of matrix computations such as matrix power, multiplication, and inversion...
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