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A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50×50 μm2 and the matrix consists of 64×64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented,...
The SuperB asymmetric e+ e- collider has been designed to deliver a luminosity greater than 1036 cm-2 s-1 maintaining moderate beam currents. Comparing to current B-Factories, the reduced center-of-mass boost of the SuperB machine requires an improved vertex resolution to allow precision measurements sensitive to New Physics. Therefore the SuperB Silicon Vertex Tracker will be equipped with an innermost...
The SDR0 (Sparsified Digital Readout) prototype is a proof-of-principle design which is aimed at studying the feasibility of pixel level sparsified digital readout in CMOS MAPS matching the requirements for the Vertex Detector at the International Linear Collider. The deep n-well (DNW) available in deep sub-micron CMOS processes is used to collect the charge released in the substrate, and signal processing...
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