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This paper combines several low-leakage and low-cost techniques to design multi-port static random access memory (SRAM) for register file in a vertex shader processor for OpenGL ES 2.0 graphics applications. First, precharge control is employed to eliminate unnecessary precharge operations. Then, dynamic forward body-bias control for leakage reduction is proposed to adjust the threshold voltage of...
Companies recognize the need to be customer driven by providing superior service to satisfy customers' needs. But as customers and their needs grow increasing diverse, unnecessary cost and complexity are inevitably added to operations. This paper introduces a new application customization method with a new UI layout markup language as well as an UI layout algorithm. The mobile client generates web...
One of the most important issues during the analog layout phase is to achieve accurate capacitance ratios. However, systematic and random mismatches will affect the accuracy of the capacitance ratios. A common-centroid placement is helpful to reduce the systematic mismatch, but it still needs the property of high dispersion to reduce the random mismatch [10]. To deal with this problem, we propose...
A fully differential 60 GHz three-stage transformer-coupled amplifier is designed and implemented in 65 nm digital CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanisms, and simultaneous input/inter-stage/output matching networks are used to facilitate a compact circuit design. With a cascoded circuit configuration, the amplifier is tested...
To reduce parasitic mismatches in analog design, we usually care about the property of symmetric placement for symmetry groups, which would form several symmetry islands in a chip. However, routing is greatly affected by placement results. If modules with input or output ports are placed arbitrarily in a symmetry island, the routing wires, which connect these modules with other modules outside the...
In this paper, we present a low dropout voltage regulator (LDO) which can be programmed to generate four output voltages (3.3 V, 2.5 V, 1.8 V, and 0 V) by the external control signals. Between the error amplifier and the power transistor, we place a simple buffer so that the power supply rejection (PSR) of LDO can be improved. The design specification of the maximum load current is 100 mA. The proposed...
This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). The design variables of the component sizing are bias voltages and bias currents. The free space of the variables is easy to be restricted by circuit constraints. A lookup-table-based scheme is presented to translate the variables...
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