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In shortening based coding design, a certain amount of known information bits (for instance, all 0 bits) will be inserted into each information packet for encoding and be removed before transmission. Since they are known, the decoder can assume a complete codeword in decoding, even those known bits are not delivered at all. Basically, shortening provides a framework to generate a set of more powerful...
A data reconstruction scheme for the storage code that possesses the combination property (CP) and zigzag decod-able (ZD) is proposed for distributed storage system. (n, k) CP is defined as follows: k message with each containing L bits are encoded to n ≥ k packets and then stored into n storage nodes, respectively. Any k from these n storage nodes can recover the original message. The code operates...
In this paper, a simple, efficient, low power off-chip memory design is proposed, which fully exploits the features of DRAM memory and video application, as well as overcomes the drawbacks of algorithm complexity and system modification of embedded compression, which is a popular way to decrease power consumption of the off-chip memory. The integration of the scheme into video decoder will not involve...
H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization, and can be used to fit well with the requirements for this decoder. To simulate and evaluate...
This paper presents a design of 8B/10B encoder and decoder with a new architecture. The proposed 8B/10B encoder and decoder are implemented based on pipeline and parallel processing. The decoder implements an error-undiffusing function. This 8B/10B encoder and decoder can be used in the high-speed interconnection between chips. After being synthesized using CMOS 90nm process, the proposed encoder...
In this paper, a functional model of SystemC-based MPEG-2 decoder is presented, which is of heterogeneous multi-IP-cores and hybrid-interconnections. Considering the application-specific features into the design flow, three important aspects are analyzed, including function partition, parameter sharing, and interconnection topology, which are the key technical difficulties in the system level design...
A highly integrated system-on-chip (SOC) can be a viable replacement for a design based on legacy X86 series based design. Embedded processors for aviation field and industrial controls are the examples for aforesaid proposal. To reduce the high volume of old system, we design and implement a SOC embodying a low power X86 instruction compatible 32-bit CISC microprocessor. Outside the processor core,...
In this paper, we propose a cost-effective scheme for robust wireless multi-party video conferencing based on network coding (NC). The main idea is the adoption of a NC scheme to enhance robust transmission, to simplify the erasure protection procedure, and to reduce the downlink bandwidth by leveraging the properties of opportunistic NC and wireless broadcasting. We design a pipelining schedule to...
This paper presents a reversible data embedding scheme with prediction and dissimilar techniques for palette-based images. Two embedding rules are imported in the proposed method, and no extra bit map is required to indicate which rules are applied in which pixels to embed secrets. As the experimental results show, when the hiding capacity is 255 Kb, the visual quality of the decoded image for our...
In most data-hiding schemes, the area of interest in the cover image cannot be protected from being modified. In this paper, we propose a data-hiding scheme in which the changeable and unchangeable pixels can be specified by the data-hider. To reduce the size of extra information, the location map used to depict the location information of changeable and unchangeable pixels is compressed by Run Length...
A Blue-ray Disc (BD) player, back-end SoC supporting multiple protection, video and display formats is fabricated in a 90 nm 1P7M CMOS process with a core area of 62.95 mm2. This SoC adopts a general copy protection (GCP) unit to integrate various kinds of protection algorithms (e.g. AES, CSS, CPPM/CPRM, DES, SHA-1/MD5), designs a dedicated memory management unit (MMU) for realizing multiple video...
A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal...
Parametric stereo is a state-of-the-art stereo coding method. It can efficiently encode a stereo audio signal into two parts including a monaural signal and small amount of stereo parameters. In this paper, the implementation of parametric stereo in digital radio mondial (DRM) system is presented. And the difference between parametric stereo in DRM and MPEG-4 is also discussed. Using parametric stereo,...
The appearance of the new AVS standard offers opportunities for low power implementations of video encoders and decoders suitable for a wide range of mobile applications. AVS is the recent video coding standard developed by the Audio and Video Coding Standard Workgroup of China, which promises similar performance but lower complexity compared with H.264. This paper presents the complexity analysis...
A major bottleneck of MP@HL MPEG-2 decoder is the memory bandwidth. It is important to improve the utilization ratio of the memory bandwidth in MPEG2 decoder. To realize it, a new memory storing architecture is proposed in this paper. Since the number of overhead cycles needed for row-activations in SDRAM can be minimized, the memory bandwidth can be improved significantly. Compared with the linear...
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