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The performance of logic function could be affected significantly by the noise effect as the dimension of CMOS devices scales to nanometers. Thus, many pertinent researches about noise-tolerant logic gate have received growing attention. Considering the randomness as the noise's nature, probabilistic-based approach proves better noise-immunity and three design schemes with the technique of Markov...
Multi-stage latency adders based on different prediction schemes have been proved promising to enhance the circuit performance with negligible overhead. This paper presents a novel predictor exploiting both the detection and the sequence-dependence between the successive calculations. The detection of carry-kill pattern of the input data can lower the probability of the operation with multiple clock...
With the rapid increase of automobile holdings in the domestic, how to effectively manage vehicles in regional range and improve the effective utilization of limited resources are problems that cannot be ignored by the team managers. In order to solve the above problem, this thesis takes “Peace travel” ubiquitous network demonstration system as the background, based on the technology of Flex, proposes...
A novel low-power and high-speed master-slave D flip-flop (MSDFF) is proposed in this paper. Without clocked inverter on critical path, the flip-flop operation speed has been improved. Employing the pseudo-NAND logic in the slave stage, the flip-flop has a smaller clock capacitance load, which helps to reduce the power consumption. The proposed flip-flop is verified with GSMC 1.5 V-0.15 mum CMOS technology...
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