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The circuit presented is a power-efficient implementation of a 16 Gb/s I/O link NRZ receiver in 22 nm CMOS SOI. A CTLE feeds an 8-tap DFE for ISI equalization. The first tap uses digital speculation and the following seven taps are realized with switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud rate CDR. The receiver architecture is half rate...
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