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This paper focuses on the monitoring and debugging issues of concurrent DSP processing system in real time large scale distributed parallel scenario. It strives for putting the record and replay technique which stems from the parallel computing realm, into practice for modern high performance embedded computing (HPEC) application and enhancing its feasibility and scalability. Architecture of event...
The demand from radar application and the key technique on real-time net-booting a large-scale DSP network is substantially analyzed. In the large-scale scenario, we have scrutinized the booting performance and constructed a real-time net-booting system, an inexpensive implementation with it. In the end of the paper, a practical application via TigerSHARC DSP processor is introduced
Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result...
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