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Due to the spatial-locality property of data caches and the temporal-locality property of instruction caches, significant leakage reduction can be achieved by switching a large number of cache lines into the low-power standby or drowsy mode. It has been shown that 80%-90% of the data cache lines can be maintained in drowsy state without affecting the performance by more than 0.6% (IEEE Trans. Very...
With the introduction of the drowsy cache design technique (Kim et al., 2004), new fault behaviors appear and more restrictive design rules must be applied to the chip fabrication process. In this research, we simulate all possible spot defects (SDs) under normal mode and drowsy mode in different resistance regions using HSpice. Six new fault models appear with the introduction of drowsy mode for...
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