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The experiments and results of these calibation campaigns in the frame of APMP from 2014 to 2016 have been reported and the experiment setups and the corresponding delay measurements have been discussed, and the uncertainty has been evaluated for the campaigns.
In recent years, there has been a dramatic demand for stringent time/phase synchronization due to the continuing evolution of mobile network technologies. The primary reference time clock (PRTC) located in core centers provides reference time and phase synchronization signal traceable to a recognized time standard UTC(*) for other clocks within the telecommunication networks. The performance monitoring...
In this paper, we propose a new generation of time and frequency transfer system using Global Navigation Satellite System (GNSS) dual frequency receiver for the purpose of both time and frequency synchronization. The system can be used as a timing source, remote time and frequency calibration, and to monitor the characteristic of the telecommunication primary reference clocks (PRC). A series of experiments...
The measurement of the signal propagation delay is essential for positioning, navigation and timing applications. In this paper, we proposed a new method, transmitting the multi-carrier pseudorandom noise (PRN) signals and measuring the group delay as the precise signal propagation delay by weighted least squares (WLS) technique, so that the bandwidth can be more effectively utilized. The platform...
A new remote time and frequency calibration system using Global Positioning System (GPS) common-view or all-in-view method for the purpose of time synchronization and frequency syntonization is presented. The system integrates GPS timing receiver with measurement hardware and software. It can be used as Primary Reference Clock (PRC), remote time and frequency calibration, and monitoring the characteristic...
This work presents a new frequency plan and a reconfigurable 6.6 / 7.128 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with integrating differential switchable inductors. Based on this frequency plan, a further simple synthesizer architecture is proposed with only two PLL's, two mixers, and one multiplexer. The QVCO is implemented with the mutual-coupling structure of two differential LC-tuned...
An integrated switchable inductor with symmetric differential layout is proposed. It can be achieved over 50% area shrinkage as compared with the traditional ones. Three testkeys with a typical switch-ON inductance of about 2.1 nH (at 1.8 GHz) were pre-designed using an electromagnetic simulator and successfully verified by TSMC's 0.18 mum RF CMOS technology. The measured ON/OFF inductance values...
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