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Nonvolatile (NV) processors have attracted much attention in recent years due to their zero standby power, resilience to power failures, and instant-on feature. One design challenge of NV processors is the excess area needed by NV registers. This paper introduces a parallel compare and compress (PaCC) architecture to reduce such excess area. A key component of the PaCC architecture is a new codec...
In modern embedded systems, the C2RTL (high-level synthesis) technology helps the designer to greatly reduce time-to-market, while satisfying the performance and cost constraints. To attack the performance challenges in complex designs, we propose a FIFO-connected hierarchical approach to replace the traditional flatten one in stream applications. Furthermore, we develop an analytical algorithm to...
Vehicle-based pedestrian detection systems play a very important role in the field of intelligent transportation. However, existing pedestrian detection algorithms are too computing extensive for traditional vehicle-based processor. Considering the performance and flexibility of hardware/software co-design architecture (CPU+FPGA), it is feasible to implement these algorithms on such platforms. In...
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