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Process induced variations in the interconnect capacitance and resistance have resulted in significant uncertainly in the interconnect delay. In this work, we propose a new method to compute the interconnect corner considering coupling-noise due to simultaneous switching of aggressors. In prior approaches, the interconnect corners were computed under the assumption that the aggressor nets are not...
This work implements a switched-capacitor block, that isolates the switching activity by equalizing the current drawn from the encryption core to secure an AES engine. An array of capacitors provides the supply current for the sensitive blocks of the encryption engine while non-sensitive blocks run directly from the supply. Each capacitor is charged from the supply and is then isolated while it provides...
Digital circuits operating at subthreshold-voltage levels can achieve extremely low energy consumption. Typical applications include sensor processors with modest processing requirements that must run for long intervals on a low energy supply. The design goal is to minimise the total energy required for a processing task. Optimal architectures strike a balance between leakage and dynamic dissipation:...
In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance...
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