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In this paper, the potential of Tunnel FETs (TFETs) for ultra-low power operation is investigated in the context of digital circuits operating below 500 mV. A comparative analysis of TFETs and SOI CMOS in 32 nm technology is performed through device-and circuit-level simulations, based on a unitary simulation framework where all devices are fairly designed for the same (low) voltage range and the...
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