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HfO2 gate dielectric is fabricated by atomic layer deposition on an n-type germanium (Ge) substrate to form p-type Ge MOS capacitors. Three solution-based chemical treatments of the Ge surface using propanethiol, octanethiol and (NH4)2S solutions respectively as well as post-metallization annealing are investigated to improve the interface quality of HfO2 gate dielectric on the Ge substrate. Experimental...
This paper describes the development of work function measurements using Kelvin probe force microscopy (KPFM) on semiconductor materials including high-κ/metal gate layers. We show how the choice of substrate and/or underlying films affects work function quantification. Other influences on work function measurement such as sample aging, humidity, and measurement mode were also studied. Finally, TiAl...
This paper describes the development of work function measurements using Kelvin probe force microscopy (KPFM) on semiconductor materials including high-κ/metal gate layers. We show how the choice of substrate and/or underlying films affects work function quantification. Other influences on work function measurement such as sample aging, humidity, and measurement mode were also studied. Finally, TiAl...
This paper reports on the low-dose-rate radiation response of Al-HfO2/SiO2–Si MOS devices, where the gate dielectric was formed by atomic layer deposition with 4.7 nm equivalent oxide thickness. The degradation of the devices was characterized by a pulse capacitance-voltage (CV) and on-site radiation response techniques under continuous gamma ($\gamma $ ) ray exposure at a relatively low-dose-rate...
Titanium-aluminum (TiAl) alloys are the industry standard source for work function tuning of High-K nMOS transistors in the gate-last process architecture. When aluminum is used as a metal gate fill material, the TiAl alloy also serves as a diffusion barrier against excess aluminum migration into the work function metal and dielectric layers. However, the formation of the TiAl alloy by annealing titanium...
This paper reports the investigation of constructing 50-ohm microwave transmission lines in a commercial 90-nm CMOS process with multi-level metallization. A semi-enclosed stripline design based on the conventional microwave stripline structure is proposed for silicon monolithic microwave integrated circuits. The design has been verified by electromagnetic simulation with a low insertion loss of 2...
This paper reports the frequency response measurements and equivalent circuit modelling of a piezoelectric ultrasonic atomizer device. It aims to examine the perpetual-operation performance of piezoelectric ultrasonic transducers in atomization applications. The resonance frequency of a water-loaded atomizer device is found to remain virtually unchanged in perpetual operation of less than 100 hours...
A low-cost design of millimeter-wave absorbing sheets is investigated. The absorber is composed of a perforated resistive film on a flexible polyethylene terephthalate (PET) substrate which is backed by a resistive ground plane. Broadband (60 GHz to 120 GHz) and wide-angle (up to 80°) absorption (> 50%) is achieved for a design with a square lattice of circular holes (diameter d = 5.5 mm and lattice...
A compact transmission line design based on the conventional microwave stripline is presented for implementation of millimeter-wave CMOS integrated circuits. In a 65-nm process, the design gives a low insertion loss of 2.2 dB/mm at 60 GHz as determined by 3D electromagnetic (EM) simulations. A 50-Ω characteristic impedance is achieved resulting in a reflection coefficient of about −27 dB up to 80...
This paper reports an exploratory study of implementing microstrip lines in flexible electronics technology by printing conductive tracks on flexible polyethylene terephthalate (PET) films. Based on the material properties of inkjet printable nanoparticles and of PET films published in the literature, electromagnetic-field simulations with COMSOL are used to determine the radio-frequency (RF) performance...
Effects of 137Cs gamma irradiation on the DC electrical characteristics of InAs/GaAs quantum dots (QDs) mesa diodes are reported. The devices were irradiated with gamma-rays for different doses ranging from 100 rad to about 1 Mrad (GaAs). The QDs mesa diodes are found to be tolerant to γ radiation. No enhanced leakage current and shift in the turn-on voltage were observed in the InAs/GaAs QD devices...
Copper metal gate has been introduced in logic CMOS processes starting from the 45-nm technology node. With the skin depth of about 270 nm at 60 GHz for copper, the DC end-to-end resistance of the copper gate electrode is found to be Rdc ≈ 9 Ω for a 45-nm MOSFET with W/L = 30 and it is a good estimation of the actual effective resistance Rac with less than 1% error. Rac of copper-gate electrode with...
The effect of parasitic capacitances and resistances on RF performance is investigated for a recently reported 30-nm transistor with regrown source and drain structure which is to reduce the access resistance in nanoscale MOSFETs. The relatively large lateral parasitic capacitances from the gate electrode to the regrown source and drain regions are quantitatively determined to estimate their impact...
A recently reported nanometre-scaled MOSFET structure with regrown source and drain is examined. The parasitic circuit elements are identified and quantitatively determined to estimate their impact on the transistor's RF performance. Due to the relatively large lateral parasitic capacitances from the gate electrode to the regrown source and drain regions, the current gain cut-off frequency fT of such...
Spansion's facility in Austin, Texas USA has proactively been updating the older AI technology fab with state-of-the-art control systems, as driven by rapid response to exposed Cu experiences from the latest in Cu technology. This paper discuss the positive and negative in-line and material observations with processing Cu in open cassettes; the manufacturing operations queue time affects; along with...
In an attempt to increase polisher throughput and reduce slurry costs at STI CMP, modifications to the HDP oxide deposition step were conducted. This was done after observing a reduced time to planarize a wafer with thicker oxide. Vertical scanning Interferometry was used to aid in understanding the wafer surface topography as a function of the HDP oxide deposition. Wafers deposited with 17000A of...
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