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In this paper, a low power delay locked-loop with modified voltage-controlled delay cell (VCDC) is proposed. This modified VCDC is designed by using Mentor Graphic CEDEC design kit and Silterra 0.13μm process technology. Thus, the DLL with proposed VCDC able to obtained low power dissipation which is 921.57μW and occupied very smaller area which is 0.03mm2.
The paper demonstrates the circuit of a low power D flip-flop serial in/parallel out (DFF SIPO) based shift register design. The flip-flops (FF's) consumption of casual logic power in a SoC chip (system on chip) commonly overpasses 50% as long the input and the output are in the same state thanks to the redundancy transition of interior loops. Conventional implementation of shift register systems...
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