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In this paper, a low power delay locked-loop with modified voltage-controlled delay cell (VCDC) is proposed. This modified VCDC is designed by using Mentor Graphic CEDEC design kit and Silterra 0.13μm process technology. Thus, the DLL with proposed VCDC able to obtained low power dissipation which is 921.57μW and occupied very smaller area which is 0.03mm2.
Low noise and low Power transimpedance amplifiers (TIA) are essential module for optical sensor based systems. But low power and low noise TIAs are still a challenge for the scientists despite of rapid advances in complementary metal oxide semiconductor (CMOS) technology. This paper proposes a three-stage nested miller compensated (NMC) based design of low noise low power transimpedance amplifier...
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