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This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 50 ps time resolution, and the ranges of differential...
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