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A feasibility study was carried out for self-formation of metal wiring between LSI chips containing ultrafine-pitch Cu landing pads by employing a new concept of directed self-assembly (DSA) phenomena. Preliminary results suggest that it is highly feasible to electrically interconnect two LSI chips having Cu landing pads at 3μm pitch interval. Electrical contact between the flip-chip bonded dies was...
Effects of electro-less Ni layer as barrier/seed layers were evaluated for high reliable and low cost Cu TSVs. To electrically characterize the effectiveness of a Ni layer as barrier/seed layers for TSV application, we fabricated the trench MOS capacitor with 5µm dia. and 50µm depth TSV array. Via holes were successfully filled by Cu electro-plating by using Ni seed layer. To characterize the blocking...
Reliability challenges in 3D LSI associated with mechanical constraints induced by Cu TSVs, μ-bumps and crystal defects, crystallinity in thinned Si wafer and metal contamination induced by Cu diffusion from TSVs and thinned backside surface are mainly discussed. Mechanical stresses induced by Cu TSVs and μ-bumps are strongly dependent on design rules and process parameters. DRAM retention characteristics...
3D integration is the most promising technology to enhance LSI performance beyond scaling theory. 3D LSIs have lots of advantages such as short wiring length, small chip size, and small pin capacitances, which leads to low power dissipation and high processing speed. However, there are still reliability problems to be solved. This paper describes mechanical stresses caused by Cu TSVs and CuSn microbumps...
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