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Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized...
The phase noise of a phase-locked loop (PLL) has a great impact on the performance of frequency-modulated continuous-wave (FMCW) radar. To examine the effects of the phase noise on FMCW radar performance, a model of an FMCW radar with a noisy PLL is developed. A filter-based technique for modeling the PLL phase noise is described. The radar model shows that PLL in-band phase noise affects the spatial...
A time-to-digital converter (TDC)-based skew compensation technique is proposed to minimize timing skew between main and pre-emphasis signals of high-speed current mode output driver. Skew between signals of main and pre-emphasis branches of output driver increases jitter. The proposed technique measures and compensates the timing skew to reduce the jitter in the output data. With the compensation...
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