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In this paper, the influence of the possible silicon interposer 2.5D stacking strategies on the micro-architecture of an interconnect topology is studied. We present case studies at different chip scales, based on active CMOS interposers using synchronous or asynchronous NoCs or point to point links, passive metal interposers with DC lines or RF microstrip lines, and optical interposers using multipoint...
Current VLSI systems-on-Chips (SoCs) integrate billions of transistors and are clocked with multi-gigahertz clock frequencies. As the geometrical dimensions of both devices and wires in theses systems become smaller, the internal communication performance between the SoC's blocks is heavily affected by the on-chip interconnect wire delays. In this paper, we propose a high efficient mesochronous outfit...
Flip-flops with output enable are crucial elements for the design of digital systems. With the aggressive scaling in feature sizes, they start to pose some challenging problems for designers. This is due to their synchronous nature that represents the main cause of both the high digital noise that they generate and the significant fraction of power that they consume essentially dynamically. In this...
In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for low-power and low-noise on-chip devices. The device is constructed around a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics...
In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65nm process...
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