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In this paper, we propose the design method and the structure of a decoder with shortened cyclic code for radio data systems (RDS). Without microprocessor the logic gates are used to implement the hardware of the decoder, moreover, the decoder not only can decode the received message of RDS, but also has the functions of synchronization, error detection and error correction. The proposed decoder includes...
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain...
In this paper, a combined Low-Density Parity- Check (LDPC) code decoding design method, called modified Block-Type LDPC (B-LDPC), for realistic LDPC coding system architectures is presented. The B-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular...
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