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We present an attractive poly-SiGe thin film packaging and MEM (Micro Electro-Mechanical) platform technology for integrating various packaged MEM devices above standard CMOS. The packages, having cavities as large as 1 mm2, make use of pillars designed to withstand subsequent molding during 1st level packaging. Covers on top of the release holes avoid deposition inside the cavity during sealing....
A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3times10-10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write...
In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle...
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