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A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A novel deep trench isolation (DTi) process module enables an isolated pwell (IPW) bias scheme, leading to flash with uniform channel program/erase (UCPE) by Fowler-Nordheim (FN) tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly...
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