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The recent adoption of OpenCL programming model by FPGA vendors has realized the function portability of OpenCL workloads on FPGA. However, the poor performance portability prevents its wide adoption. To harness the power of FPGAs using OpenCL programming model, it is advantageous to design an analytical performance model to estimate the performance of OpenCL workloads on FPGAs and provide insights...
Iterative stencil algorithms find applications in a wide range of domains. FPGAs have long been adopted for computation acceleration due to its advantages of dedicated hardware design. Hence, FPGAs are a compelling alternative for executing iterative stencil algorithms. However, efficient implementation of iterative stencil algorithms on FPGAs is very challenging due to the data dependencies between...
This paper proposes a fuzzy logic PID based control method for a biomimetic underwater vehicle on swimming speed and yaw angle. The vehicle has a pair of long-fins installed symmetrically on its body. A set of inertial sensors are applied for collecting its velocity and pose information. And an embedded control system and a driving system based on FPGA are designed for generating and switching motion...
This paper has investigated present radiation hardened FPGA manufacturers and SEU hardened method of configurable SRAM (CSRAM) applied to FPGA. A novel high-density single-event upset hardened CSRAM applied to BQV 300 FPGA is proposed, and this paper uses the mix-mode radiation hardened verification method to simulate the SEU hardened CSRAM. The proposed SEU-hardened CSRAM applied to FPGAs is SEU...
Motion control for one kind of underwater robotic fish is presented in this paper. Here our robotic fish prototype has two long-fins installed symmetrically on its both sides. And one long-fin is made up by springiness membrane covered on ten ray-fins. Ten servo-motors are used to control the motions of the ten ray-fins on one side. Due to the special structure of the prototype, swimming motion modes...
Field programmable gate arrays (FPGAs) is becoming one of the most widely used electronics devices. Because of its unique architecture, power estimation is a complicated task for FPGAs. This paper presents a novel power estimation framework for SRAM-based FPGAs. Considering both dynamic power and static power, a gate-level power model for configuration logic blocks (CLBs) and a transistor-level power...
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