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Reducing the operating voltage of digital systems improves energy efficiency, and the minimum operating voltage of a system ($V_{\min }$ ) is commonly limited by SRAM bitcells. Common techniques to lower SRAM $V_{\min }$ focus on using circuit-level periphery-assist techniques to prevent bitcell failures at low voltage. Alternatively, this paper proposes architecture-level techniques to allow caches...
The presented processor lowers SRAM-based cache Vmin by using three architectural techniques-bit bypass (BB), dynamic column redundancy (DCR), and line disable (LD)-that use low-overhead reprogrammable redundancy (RR) to avoid failing bitcells and therefore increase the maximum bitcell failure rate in processor caches. In the 28nm chip, the Vmin of the 1MB L2 cache is reduced by 25%, resulting in...
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