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Asymmetric and independent gate features of DGMOSFETs are explored recently for nano scale applications. This paper investigates minimization of short channel effects based on the independent gate, gate-S/D under lap and asymmetric (in front and back gate oxide thickness, gate work functions and gate bias) features of DGMOSFETs. Novel analytical models for threshold voltage, threshold voltage roll-off...
Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be...
A novel analytical model for subthreshold slope of a generic double-gate MOSFET (DGMOSFET) with gate-to-source/drain underlap is proposed. The accuracy of the new model is verified based on comparisons with previously published models, experimental data and numerical simulation results. With the reduction in body thickness, an improvement in underlap independent gate (4T) DGMOSFET subthreshold slope...
A novel analytical model for subthreshold current of a generic double-gate MOSFET (DGMOSFET) with gate-to-source/drain underlaps is proposed. The accuracy of the new model is verified based on comparisons with previously published models and numerical simulation results. With the proposed current model, effectiveness of back gate biasing, back gate asymmetry, gate work function engineering, and gate...
Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic...
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