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This paper deals with the design and analysis of 1Kb Static Random Access Memory (SRAM) at 180nm, focusing on optimizing power and delay. The entire SRAM can be divided into 4 blocks with each block having equal capacity of 256b. The key of low power operation in the SRAM is to reduce the wordline capacitance. The sense amplifier is placed below the column decoder circuit. Here only one sense amplifier...
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