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With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13-mum CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer...
This work presents a mixed-voltage I/O buffer realized with 1/spl times/V/sub DD/ devices and single V/sub DD/ power supply to receive 3/spl times/V/sub DD/ input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13 /spl mu/m 1V CMOS process. This technique can be extended to receive 4/spl times/V/sub DD/, 5/spl times/V/sub CD/, and even 6/spl times/V/sub...
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