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In this paper, electrostatic discharge (ESD) protection circuit with an advanced substrate-triggered NMOS and a gate-substrate triggered NMOS using PNP bipolar transistor are proposed to provide low trigger voltage, low leakage, and fast turn-on speed. The experimental result show that the proposed substrate-trigged NMOS has a low trigger voltage of 5.98V and faster turn-on time(∼37ns). The proposed...
This paper presents a novel silicon controlled rectifier (SCR)-based (Electrostatic Discharge) ESD protection devices for I/O clamp and power clamp. The proposed ESD protection devices has a high holding voltage and a low tigger voltage characteristic than conventional SCR. These characteristics enable to latch-up immune under normal operating conditions as well as superior full chip ESD protection...
ESD Protection circuits with low triggering voltage, low leakage current and fast turn-on using trigger techniques are presented in this paper. The proposed ESD protection devices are designed in 0.13um CMOS Technology. The results show that the proposed substrate Triggered NMOS using bipolar transistor has a lower trigger voltage of 5.98V and a faster turn-on time of 37ns. And the results show that...
In this paper, a Self-Aligned device using Vertical Nitride (SAVEN) having 43 ps/gate is proposed. To obtain the faster switching speed SAVEN adapted several technologies, such as the reduction of extrinsic base width, trench isolation, and emitter polycidation process. The emitter area was designed with 1.0 ?? 4.0 um**2.
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