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Twisted-ring-counters (TRCs) have been used as built-in test pattern generators for high-performance circuits due to their small area overhead, low performance impact and simple control circuitry. However, previous work based on a single, fixed-order TRC often requires long test time to achieve high fault coverage and large storage space to store required control data and TRC seeds. In this paper,...
This paper proposes a new test-per-clock BIST method that attempts to minimize the test sequence length and the test data volume simultaneously. An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect the maximum number of so far undetected faults. During the seed determination process an adaptive X-filling process is first employed...
Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudo-random and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in...
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