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In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). Back-gate engineering is introduced to reduce the series resistance and threshold voltage shifts. We show that short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.
In this paper, we analyze LDD depletion effects in fully-depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15 nm.
We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.
In this paper, we report the possibility of achieving sub-kT/q subthreshold slope (i.e. lower than 59.6 mV/decade at T=300 K) without using either impact ionization or band-to-band tunneling. The device uses intraband tunneling within the conduction band through barriers whose shape varies with the applied gate voltage. Subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported...
The results are reported of an experimental study of the hot carrier (HC) and bias-temperature-instability (BTI) reliability of MuGFETS, fabricated on SOI wafers with silicon oxide and silicon nitride buried layers. N- and P-channel devices of 65 nm long and 42 nm or 32 nm wide channels were stressed and measured at room temperature and at 125degC. A complicated picture emerges: HC degradation is...
We have investigated the effect of symmetric geometrical constrictions on the device characteristics of ultrathin silicon-on-insulator (SOI) nanowire with Trigate structure by means of the full real-space three dimensional Nonequilibrium Greens's Function (NEGF) method. In this study, geometrical constrictions are introduced as energy barriers near the source and the drain junctions and their strength...
This work studies the influence of gate misalignment on the electrical properties of MuGFETs using both measurements and 3D simulations. Electrical characteristics such as a DIBL, Vth and drain breakdown voltage are shown to be dependent on the gate misalignment due to the resulting change in fin width. Devices that have a Widening of the fin at the Drain side (DW) decreased due to weakening of gate...
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