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In this paper, we analyze LDD depletion effects in fully-depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15 nm.
In this paper, we report the possibility of achieving sub-kT/q subthreshold slope (i.e. lower than 59.6 mV/decade at T=300 K) without using either impact ionization or band-to-band tunneling. The device uses intraband tunneling within the conduction band through barriers whose shape varies with the applied gate voltage. Subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported...
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