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This paper proposes a 3 GHz built-in jitter measurement (BIJM) circuit to measure clock jitter on high-speed transceivers and SoC systems. The proposed BIJM circuit adopts a high timing resolution and self-calibration techniques and discusses the measurement error issues. The measurement error source is analyzed each block in BIJM. To eliminate process variation effects in 3 GHz systems, this study...
This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the...
A high-speed current mode sense amplifier for Spin Torque Transfer Magnetic Random Access Memory (STT MRAM) is proposed. The sense amplifier is designed in a 0.18 μm CMOS technology, and 1.8 V supply voltage. The resistance values of high state is 2132 Ω, low state is 1215 Ω, and reference state is 1512 Ω, respectively. The proposed sense amplifier decreases the dropping rate of input bias. In particular,...
This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon...
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