The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a...
TSV interposer provides a cost efficient solution way for 3D IC integration. In this paper, a TSV interposer technology is proposed for SRAM stacking. A simple fabrication process is developed for cost-sensitive application. The mushroomlike Cu/Sn bumps by copper overburden can be directly connected with other substrate, which eliminates a CMP planarization to improve the yield and reduce fabrication...
The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presented in this paper. BCB is selected as the passivation layer and the electroplated Cu is used as the metal layer. CYCLOTENE 3024–46 is utilized and it is deposited by spin-coating and soft cure at 210 °C in annealing oven for 40 minutes with N2 protection. Sputtered Ti/W/Cu and electron beam evaporated...
In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.
This paper focused on the process of forming sidewall insulation of through silicon via (TSV) which was a challenging bottleneck in 3D integration technologies. In traditional way, etching silicon oxide on via bottom would reduce the thickness of sidewall insulation layer inevitably, which might lead to the failure of TSV sidewall insulation and electrical interconnection characteristic. In this paper,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.