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Varactors can be used to control delays and limit ISI-related signal integrity degradation for on-chip global interconnect. This paper presents a varactor-based “near-speed-of-light” interconnect design. In this design, the varactors compensate for delay variations enabling a simple, source-synchronous solution for clock-and-data recovery. Furthermore, the varactors provide pulse shaping that reduces...
Synchronizer characterization is non-trivial. The exponential response to parameter changes makes this task a challenge, which is further hampered by numerical instability and precision limitations of circuit simulators. The analysis of multi-stage synchronizers is extremely difficult due to the compounding of these exponential factors. We present results and discoveries from analyzing a variety of...
System-on-chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchronizers must be characterized accurately to ensure the robustness of the complete system. We present a novel approach for determining the failure probabilities of synchronizer circuits. Our approach use numerical integration...
A long chain of inverters and wire segments will amplify clock jitter and drop timing pulses due to intersymbol interference. We present a jitter attenuating buffer based on surfing techniques. Our buffer circuit consists of a few inverters with variable output strength that implement a simple, low-gain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous...
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