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We report our results on pulse-forming-line (PFL)-based CMOS pulse generator studies. Through simulations, we clarify the effects of PFL length, switch speed, and switch resistance on the output pulses. We model and analyze CMOS pulse generators with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In a 0.13- m CMOS process with a 500- m long PFL, post-layout simulations...
We report our results on pulse forming line (PFL) based CMOS pulse generator studies. Standard on-chip transmission lines are used as PFLs while CMOS transistors are used as switches. Through simulations, we clarify the effects of switch speed and switch resistance on the generated pulses. In a standard 0.13 μm CMOS process with a 500 μm long PFL, post layout simulations show that pulses of 10.4 ps...
This paper presents low power circuit design for voltage regulator and resistor to digital converter that are used in a RFID-like sensing circuit for measuring the resistance of a sol-gel sensor. The regulator circuit has simple circuit structure and consumes zero DC current (except the current drained by its load). The resistor to digital converter consists of a cascoded current mirror, a reference...
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