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A novel physical unclonable function (PUF) that based on random telegraph signal noise (RTN) is proposed and studied in this work. Firstly, systematical experiments have been done in ultra-scaled devices with various gate stack structures. It is found for the first time that strong correlations between trap time constants and thermal activation energies universally exist in all devices, no matter...
Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while...
In this letter, hole mobility characteristics in Si gate-all-around nanowires on (110)-oriented silicon-on-insulator substrate have been studied, based on the advanced split C-V method. Fabricated nanowires have rectangular shape, and the height is fixed to 18 nm. High hole mobility in [110]-directed nanowires (widths ranging from 25 to 68 nm) were observed, illustrating 2.4 X enhancements over the...
Systematic study on hole mobility in gate-all-around (GAA) multiple Si nanowire (NW) pFETs on (110) SOI is presented for the first time. [110]-NWs show high mobility, 2.4times enhancement over universal (100) mobility, even in high Ninv region and in narrow (25 nm) NWs. Furthermore, effects of uniaxial tensile stress are also investigated, indicating that [110] direction uniaxial stress is effective...
Experimental investigations of silicon nanowire mobility characteristics on (100) SOI as shrinking nanowire width to sub-10 nm are reported. Accurate mobility estimations by advanced split CV method for 50~1000 nanowires are performed. For the first time, electron and hole mobility in [100]-directed nanowires are studied and compared with [110] nanowires. It is shown that both electron and hole mobility...
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