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Systematic study has been performed on carrier mobility in sub-10nm gate-all-around (GAA) Si nanowire (NW) FETs on (100) SOI. The NW height is 4 - 10nm and the minimum NW width is shrunk to 5nm. For the first time, higher hole mobility than universal mobility is experimentally observed in 9nm-wide NW and even in 5nm-wide NW, demonstrating great advantage of NW pFETs, while electron mobility degradation...
Investigations on electron mobility characteristics in gate-all-around silicon nanowire nMOSFETs on (110)-oriented silicon-on-insulator substrates have been described on the basis of the advanced split capacitance-voltage (C- V) method. It is found that the electron mobility in [110]-directed nanowires approaches and is even higher than that in [100]-directed nanowires as the nanowire width is reduced...
In this paper, uniaxial stress effects on silicon nanowire pMOSFET (NW pFET) and single-hole transistor (SHT) are described. For the first time, it is found that stress technology is still effective as mobility booster even at extremely narrow NW pFET but the effects are gradually diminished as NW becomes narrower because effective mass modulation decreases. In case of SHT, oscillation current modulation,...
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